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Programmable Sound Generator AY-3-8912
(from General Instruments data sheet)
Interfacing
Bus control signals BDIR (Bus DIRection), BC2, BC1 (Bus Control 2,1) are
generated directly by the CP1610 series of microprocessors to control
all external and internal bus operations in the PSG. While interfacing
to a processor other than the CP1610 would simply require simulating
these signals, the redundancies in the PSG functions vs. bus control
signals can be used to advantage in that only four of the eight possible
decoded bus functions are required by the PSG. This could simplify the
programming of the bus control signals to the following, which would
only require that the processor generate two bus control signals (BDIR
and BC1, with BC2 tied to +5V).
BDIR BC1 PSG Function
0 0 Inactive
0 1 Read from PSG
1 0 Write to PSG
1 1 Latch address
Architecture
The AY-3-8910/8912/8913 is a register oriented Programmable Sound
Generator. Control commands are issued to the PSG by writing to 16
registers (register addresses are expressed in octal base). Each of the
16 registers is also readable so that the
microprocessor can determine present states or stored data values. All
functions of the PSG are controlled through the 16 registers which once
programmed, generate and sustain the sounds, thus freeing the system
processor for other tasks.
The basic blocks in the PSG which produce the programmed sounds include:
Tone Generators produce the basic square wave tone
frequencies for each channel (A,B,C)
Noise Generator produces a frequency modulated pseudo
random pulse width square wave output
Mixers combine the outputs of the Tone
Generators and the Noise Generator. One
for each channel (A,B,C)
Amplitude Control provides the D/A converters with either
fixed or variable amplitude pattern. The
fixed amplitude is under direct CPU
control; the variable amplitude is
accomplished by using the output of the
Envelope Generator.
Envelope Generator produces an envelope pattern which can
be used to amplitude modulate the output
of each mixer
D/A Converters the three D/A converters each produce up
to a 16 level output signal as
determined by the Amplitude Control
In addition, there are two IO ports (A and B) to interface with the
outside world. Both ports are available on the AY-3-8910; only IO port A
is available on the AY-3-8912; no ports are available on the AY-3-8913.
Operation
The function of creating or programming a specific sound or sound effect
logically follows the control sequence listed:
Tone Generator Control (registers R0,R1,R2,R3,R4,R5)
The frequency of each square wave generated by the three Tone Generators
(one each for Channels A, B and C) is obtained in the PSG by first
counting down the input clock by 16, then by further counting down
the result by the programmed 12-bit Tone Period value.
Each 12-bit value is obtained in the PSG by combining the contents of
the relative Coarse and Fine Tune registers: bits 0-3 of the Coarse Tune
registers give the Most Significant bits, bits 0-7 of the Fine Tune
registers give the Least Significant bits.
Channel Coarse Tune Register Fine Tune Register
A R1 R0
B R3 R2
C R5 R4
Noise Generator Control (register R6)
The frequency of the noise source is obtained by first counting down the
input clock by 16, then by further counting down the result by the
programmed 5-bit Noise Period value. This 5-bit value consists of the
lower 5 bits (b4-b0) of register R6.
Mixer Control - IO Enable (register R7)
The determination of combining neither/either/both noise and tone
frequencies on each channel is made by the state of bits b5-b0 of R7.
The direction (input or output) of the two general purpose IO ports is
determined by the state of bits b7 and b6.
These bits are active low, so a 1 disables, and a 0 enables the function
b7 input enable IO port A
b6 input enable IO port B
b5 noise enable channel C
b4 noise enable channel B
b3 noise enable channel A
b2 tone enable channel C
b1 tone enable channel B
b0 tone enable channel A
Amplitude Control (registers R8,R9,R10)
The amplitudes of the signals generated by each of the three D/A
converters is determined by the contents of the lower 5 bits (b4-b0) of
registers R8, R9 and R10.
b5 Amplitude Mode (0: fixed, 1: envelope-variable)
b4-b0 4-bit fixed amplitude level
Envelope Period Control (registers R11, R12)
The frequency of the envelope is obtained by first counting down the
input clock by 256, then by further counting down the result by the
programmed 16-bit envelope period. This 16-bit value is obtained by
combining the contents of the Envelope Coarse (R12) and Fine (R11) Tune
registers.
Envelope Shape/Cycle Control (register R13)
The envelope generator further counts down the envelope frequency by 16,
producing a 16-state per cycle envelope pattern as defined by its 4-bit
counter output. The particular shape and cycle pattern of any desired
envelope is accomplished by controlling the count pattern (count up/
count down) of the 4-bit counter and by defining a single-cycle or
repeat-cycle pattern. This envelope shape/cycle control is contained in
the lower 4 bits of register R13. Each of these 4 bits controls a
function in the envelope generator:
b3 Continue
b2 Attack
b1 Alternate
b0 Hold
R13 bits Graphic representation of envelope generator output 8-)
00xx \__________________________________
01xx /|_________________________________
1000 \|\|\|\|\|\|\|\|\|\|\|\|\|\|\|\|\|\
1001 \__________________________________
1010 \/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\
_________________________________
1011 \|
1100 /|/|/|/|/|/|/|/|/|/|/|/|/|/|/|/|/|/
__________________________________
1101 /
1110 /\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/
1111 /|_________________________________
D/A Converter operation
The D/A conversion is performed in logarithmic steps with a normalized
voltage range of from 0 to 1 Volt.
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